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76
CY29976
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Features
* * * * * * * * * * * * Output frequency up to 125 MHz Supports PowerPC(R), and Pentium(R) processors 12 clock outputs: frequency configurable Configurable Output Disable Two reference clock inputs for dynamic toggling Oscillator or PECL reference input Spread spectrum compatible Glitch-free output clocks transitioning 3.3V power supply Pin compatible with SC973X Industrial temperature range: -40C to +85C 52-Pin TQFP package Table 1. Frequency Table[1] VC0_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
.
FB_SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FB_SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FB_SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
FVCO 8x 12x 16x 20x 8x 12x 16x 20x 4x 6x 8x 10x 4x 6x 8x 10x
Note: 1. x = the reference input frequency, 200MHz < FVCO < 480MHz
Block Diagram
PECL_CLK PECL_CLK# VCO_SEL PLL_EN REF_SEL DQ TCLK0 TCLK1 TCLK_SEL FB_IN DQ Sync Frz 0 1 Phase Detector LPF VCO 0 1 Sync Frz QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3
Pin Configuration
52 51 50 49 48 47 46 45 44 43 42 41 40 VSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 PECL_CLK PECL_CLK# VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 VSS QB0 VDDC QB1 VSS QB2 VDDC QB3 FB_IN VSS FB_OUT VDDC FB_SEL0
VCO_SEL
SELA0
SELA1
SELB0
SELB1
VDDC
VDDC
QA0
QA1
QA2
QA3
VSS
CY29976
VSS
MR#/OE Power-On Reset SELA(0,1) SELB(0,1) SELC(0,1) FB_SEL(0:2) SCLK SDATA INV_CLK 2 2 2 3 /4, /6, /8, /10 Sync Pulse Data Generator DQ DQ DQ /2, /6, /4, /12 /2, /6, /4, /10 /8, /2, /6, /4 DQ
Sync Frz
QC0 QC1
14 15 16 17 18 19 20 21 22 23 24 25 26
Sync Frz Sync Frz Sync Frz
QC2 QC3 FB_OUT
INV_CLK
VSS
QC3
VDDC
QC2
SELC1
SELC0
QC1
VDDC
QC0
VSS
SYNC
FB_SEL1
SYNC
Output Disable Circuitry
12
Cypress Semiconductor Corporation Document #: 38-07413 Rev. *A
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 27, 2002
CY29976
Pin Description[2]
Pin No. 11 12 9 10 44, 46, 48, 50 32, 34, 36, 38 16, 18, 21, 23 29 Pin Name PECL_CLK PECL_CLK# TCLK0 TCLK1 QA(3:0) QB(3:0) QC(3:0) FB_OUT VDDC VDDC VDDC VDDC PWR I/O I I I I O O O O Type PU PD PU PU PECL Clock Input. PECL Clock Input. External Reference/Test Clock Input. External Reference/Test Clock Input. Clock Outputs. See Table 2 for frequency selections. Clock Outputs. See Table 2 for frequency selections. Clock Outputs. See Table 2 for frequency selections. Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass delay capacitor at this output will control Input Reference/ Output Banks phase relationships. Synchronous Pulse Output. This output is used for system synchronization. The rising edge of the output pulse is in sync with both the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios selected. PU PU PU PU PU PU PU PU PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3) outputs. See Table 2. Frequency Select Inputs. These inputs select the divider ratio at QB(0:3) outputs. See Table 2. Frequency Select Inputs. These inputs select the divider ratio at QC(0:3) outputs. See Table 2. Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1. VCO Divider Select Input. When set LOW, the VCO output is divided by 2. When set HIGH, the divider is bypassed. See Table 1. Feedback Clock Input. Connect to FB_OUT for accessing the PLL. PLL Enable Input. When asserted HIGH, PLL is enabled. When LOW, PLL is bypassed. Reference Select Input. When HIGH, the PECL clock is selected. When LOW, TCLK (0,1) is the reference clock. TCLK Select Input. When LOW, TCLK0 is selected and when HIGH TCLK1 is selected. Master Reset/Output Enable Input. When asserted LOW, resets all of the internal flip-flops and also disables all of the outputs. When pulled HIGH, releases the internal flip-flops from reset and enables all of the outputs. Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When set LOW, the inverter is bypassed. Serial Clock Input. Clocks data at SDATA into the internal register. Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 3.3V Power Supply for Output Clock Buffers. 3.3V Supply for PLL Common Ground Description
25
SYNC
VDDC
O
42, 43 40, 41 19, 20 5, 26, 27 52 31 6 7 8
SELA(1,0) SELB(1,0) SELC(1,0) FB_SEL(2:0) VCO_SEL FB_IN PLL_EN REF_SEL TCLK_SEL
I I I I I I I I I
2
MR#/OE
I
PU
14 3 4 17, 22, 28, 33,37, 45, 49 13 1, 15, 24, 30, 35, 39, 47, 51
INV_CLK SCLK SDATA VDDC VDD VSS
I I I
PU PU PU
Note: 2. A bypass capacitor (0.1F) should be placed as close as possible to each positive power (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
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CY29976
Description
The CY29976 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125 MHz. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs, refer to Frequency Table. The VCO frequency is then Table 2. VCO_SEL 0 0 0 0 1 1 1 1 SELA1 0 0 1 1 0 0 1 1 SELA0 0 1 0 1 0 1 0 1 QA VCO/4 VCO/12 VCO/8 VCO/24 VCO/2 VCO/6 VCO/4 VCO/12 SELB1 0 0 1 1 0 0 1 1 SELB0 0 1 0 1 0 1 0 1 QB VCO/4 VCO/12 VCO/8 VCO/20 VCO/2 VCO/6 VCO/4 VCO/10 SELC1 0 0 1 1 0 0 1 1 SELC0 0 1 0 1 0 1 0 1 QC VCO/16 VCO/4 VCO/12 VCO/8 VCO/8 VCO/2 VCO/6 VCO/4 divided down to provide the required output frequencies. These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs, see Table 2 below. For situations were the VCO needs to run at relatively low frequencies and hence might not be stable, assert VCO_SEL low to divide the VCO frequency by 2. This will maintain the desired output relationships, but will provide an enhanced PLL lock range. The CY29976 is also capable of providing inverted output clocks. When INV_CLK is asserted HIGH, QC2 and QC3 output clocks are inverted. These clocks could be used as feedback outputs to the CY29976 or a second PLL device to generate early or late clocks for a specific design. This inversion does not affect the output to output skew.
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CY29976
Zero Delay Buffer
When used as a zero delay buffer the CY29976 will likely be in a nested clock tree application. For these applications the CY29976 offers a low voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance. The CY29976 then can lock onto the LVPECL reference and translate with near zero delay to low skew outputs. By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock the Tpd of the CY29976 is a function of the configuration used.
Glitch-Free Output Frequency Transitions
Customarily when output buffers have their internal counter's changed "on the fly' their output clock periods will: * Contain short or "runt" clock periods. These are clock cycles in which the cycle(s) are shorter in period than either the old or new frequency that is being transitioned to. * Contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old or new frequency that is being transitioned to. This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic levels of any or all of the following pins changed "on the fly" while it is operating: SELA, SELB, SELC, and VCO_SEL.
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CY29976
SYNC Output
In situations were output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system synchronization. The CY29976 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse depend on the higher of the QA and QC output frequencies. The following timing
VCO 1:1 Mode QA QC SYNC 2:1 Mode QA QC SYNC 3:1 Mode QC QA SYNC 3:2 Mode QA QC SYNC 4:1 Mode QC QA SYNC 4:3 Mode QA QC SYNC 6:1 Mode QA QC SYNC
diagram (Figure 1) illustrates various waveforms for the SYNC output. Note that the SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal.
Figure 1.
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CY29976
Power Management
The individual output enable/freeze control of the CY29976 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic `0' state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs can not be frozen with the serial port, this avoids any potential lock up situation should an error occur in the loading of the serial data. An output is frozen when a logic `0' is programmed and enabled when a logic `1' is written. The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial "runt" clocks. The serial input register is programmed through the SDATA input by writing a logic `0' start bit followed by 12 NRZ freeze enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK.
Start Bit
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC
Figure 2.
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CY29976
Maximum Ratings[3]
Input Voltage Relative to VSS:.............................. VSS - 0.3V Input Voltage Relative to VDD: ............................. VDD + 0.3V Storage Temperature: ................................ -65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum Power Supply: ................................................5.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
DC Parameters: VDD = VDDC = 3.3V 10%, TA = -40C to +85C
Parameter VIL VIH VPP VCMR IIL IIH VOL VOH IDDC IDD Cin Description Input Low Voltage Input High Voltage Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK Input Low Current (@VIL = VSS) Input High Current (@VIH = VDD) Output Low Voltage Output High Voltage Quiescent Supply Current PLL Supply Current Input Pin Capacitance Note 5 Note 5 IOL = 20 mA, Note 6 IOH = -20 mA, Note 6 All VDDC and VDD VDD only 4 2.4 10 15 15 Note 4 Conditions Min. VSS 2.0 300 VDD - 2.0 Typ. Max. 0.8 VDD 1000 VDD - 0.6 -120 120 0.5 Unit V V mV V A A V V mA mA pF
Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply srquencing is NOT required. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when "High" input is within the VCMR range and the input lies within the VPP specification. 5. Inputs have pull-up/pull-down resistors that effect input current. 6. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines.
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CY29976
AC Parameters:[7] VDD = VDDC = 3.3V 10%, TA = -40C to +85C
Parameter Tr/Tf Fref FrefDC Fvco Tlock Tr/Tf Fout Description TCLK Input Rise / Fall Reference Input Frequency Reference Input Duty Cycle PLL VCO Lock Range Maximum PLL lock Time Output Clocks Rise/Fall Time[9] Maximum Output Frequency 0.8V to 2.0V Q (/2) Q (/4) Q (/6) Q (/8) FoutDC tpZL, tpZH tpLZ, tpHZ TCCJ TSKEW Output Duty Cycle
[9] [9]
Conditions
Min. Note 8 25 200 0.15 -
Typ.
Max. 3.0 Note 8 75 480 10 1.2 125 120 80 60
Unit ns MHz % MHz ms ns MHz
45 2 2 100 All outputs at same frequency Outputs at different frequencies
[9]
55 10 8 350 550
% ns ns ps ps ps ps
Output Enable Time (all outputs) Output Disable Time (all outputs) Cycle to Cycle Jitter[9](peak to peak) Any Output to Any Output Skew
[9,10]
Tpd
Propagation Delay[10,11]
PECL_CLK[12] TCLK0/1
QFB =(/8)
-225 -130
-25
175 270
Notes: 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. 8. Maximum and minimum input reference is limited by VC0 lock range. 9. Outputs loaded with 30 pF each. 10. 50 transmission line terminated into VDD/2. 11. Tpd is specified for a 50-MHz input reference. Tpd is the static phase error of the device and does not include jitter. 12. VCMR = 2.0V and VPP = 650V. Tpd window will vary with different VCMR and VPP values.
]
Ordering Information
Part Number CY29976AI Package Name A52 Package Type 52-Pin TQFP Production Flow Industrial, -40C to +85C
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CY29976
Package Drawing and Dimensions
52-Lead Thin Plastic Quad Flat Pack (10x10x1.4 mm) A52
51-85131-**
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(c) Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29976
Document Title: CY29976 3.3V, 125-MHz, Multi-Output Zero Delay Buffer Document Number: 38-07413 REV. ** *A ECN NO. 114663 122922 Issue Date 05/14/02 12/27/02 Orig. of Change HWT `RBI New Data Sheet Add power up requirements to maximum ratings information. Description of Change
Document #: 38-07413 Rev. *A
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